Units:

12

Description:

This course is a second level logic design course, studying the techniques of designing at the register-transfer and logic levels of complex digital systems using modern modeling, simulation, synthesis, and verification tools. Topics include register-transfer level systems (i.e., finite state machines and data paths), bus and communication system interfacing (such as a simplified USB interface), discrete-event simulation, testbench organization, assertion-based verification and functional coverage. Design examples will be drawn from bus and communication interfaces, and computation systems, emphasizing how these systems are designed and how their functionality can be verified. A modern hardware description language, such as SystemVerilog, will serve as the basis for uniting these topics. Quizzes, homeworks and design projects will serve to exercise these topics.

Last Modified: 2024-06-27 3:46PM

Current session:

This course is currently being offered.

Semesters offered:

• Fall 2024
• Spring 2024
• Fall 2023
• Fall 2022
• Fall 2021
• Fall 2020
• Fall 2019
• Fall 2018
• Fall 2017
• Fall 2016
• Fall 2015
• Fall 2014
• Spring 2014
• Fall 2013
• Spring 2013
• Fall 2012
• Spring 2012
• Spring 2011
• Spring 2010
• Spring 2009
• Spring 2008
• Spring 2006