Units:

12

Description:

Hardware verification is the science of finding bugs in the design of computer chips. In this course, students are taught how to write effective SystemVerilog testbenches that exercise a design and its many corner cases, primarily via simulation. The Universal Verification Methodology, a blueprint for how to organize and orchestrate testbenches, is a core element of the course. Students will also be exposed to several verification metrics that together allow a verification engineer to achieve confidence that the design is bug-free. Elements of formal verification are also introduced, primarily through System Verilog Assertions. Other verification concepts, including linting, non-functional verification, analog verification, physical verification, and verification management are also covered.

Last Modified: 2025-06-30 3:22PM

Semesters offered:

• Fall 2025