Units:

12

Description:

The objective of this class is to design an ULSI (Ultra Large Scale Integrated) mobile platform and a server product in two scenarios: System on Chip (SoC) and System in Package (SiP). State-of-the-art 2016 technology nodes (28nm, 20nm or 14nm) will be assumed for the SoC scenario and full 3-D integration with Through Silicon Vias (TSV) will be pursued for the 2020 SiP scenario. Students will be given all the necessary technology data (device performance, interconnect parasitics, wafer and TSV/packaging costs, and also the expected yield data). The design objective is to deliver a product competitive to the leading products available on the market or anticipated in 5 years. The complete product design will be carried out focusing on the processor cores, graphics and the embedded memories (including new generation memories in the 2020 scenarios). System performance and power will be estimated using provided simulators for specified benchmarks. The goal is to minimize the product cost by maximizing the number of good die per wafer while achieving competitive product performance and power objectives.

Prerequisites: 18-664 or instructor permission

Last Modified: 2019-11-04 12:48PM

Semesters offered:

• Spring 2020
• Spring 2018
• Spring 2017
• Spring 2016