Units:

12

Description:

Student teams create a moderate-sized digital, analog/RF, or mixed-signal chip in a modern technology using industrial CAD tools and flows. The project involves planning and specification, writing a Verilog model, designing custom circuits and/or synthesized standard cell blocks, creating a testing/debug strategy, and full-chip integration and verification for tapeout. Completed verified designs will be sent for fabrication at the end of the semester and returned by the following fall. Students will have the opportunity to test their devices as part of a follow-on course or independent study. Recommended for PhD students that plan to design chips for their thesis, MS students interested in careers in VLSI design, or undergraduates who wish to use it to satisfy their Capstone Design requirement (requires enrollment in 18-525, see below).

This course is crosslisted with 18-525. 18-525 is the number for undergraduate students utilizing the course to complete their ECE Capstone Design requirement. Students in the graduate course number may be completing projects of increased complexity compared to 18-525.

Prerequisites: 18-622 or 18-623 or 18-422

Last Modified: 2024-11-21 4:37PM

Current session:

This course is currently being offered.

Semesters offered:

• Spring 2025
• Spring 2024
• Spring 2023
• Spring 2022
• Spring 2021
• Spring 2020
• Fall 2012
• Fall 2011
• Spring 2011