Units:

12

Description:

Student teams create a moderate-sized digital, analog/RF, or mixed-signal chip in a modern technology using industrial CAD tools and flows. The project involves planning and specification, writing a Verilog model, designing custom circuits and/or synthesized standard cell blocks, creating a testing/debug strategy, and full-chip integration and verification for tapeout. Completed verified designs will be sent for fabrication at the end of the semester and returned by the following fall. Students will have the opportunity to test their devices as part of a follow-on course or independent study. Recommended for PhD students that plan to design chips for their thesis or MS students interested in careers in VLSI design.

Prerequisites: 18-422 OR 18-622 OR 18-623, minimum grade B. Or instructor permission.

Last Modified: 2022-11-16 2:36PM

Semesters offered:

• Spring 2023
• Spring 2022
• Spring 2021
• Spring 2020
• Fall 2012
• Fall 2011
• Spring 2011