Units:

12

Description:

Student teams create a moderate-sized digital, analog/RF, or mixed-signal chip in a modern technology using industrial CAD tools and flows. The project involves planning and specification, writing a Verilog model, designing custom circuits and/or synthesized standard cell blocks, creating a testing/debug strategy, and full-chip integration and verification for tapeout. Completed verified designs will be sent for fabrication at the end of the semester and returned by the following fall. Students will have the opportunity to test their devices as part of a follow-on course or independent study. Recommended for PhD students that plan to design chips for their thesis, MS students interested in careers in VLSI design, or undergraduates who wish to use it to satisfy their Capstone Design requirement (requires enrollment in 18-525, see below).

This course is crosslisted with 18-725. 18-525 is the number for undergraduate students utilizing the course to complete their ECE Capstone Design requirement. Students in the graduate course number may be completing projects of increased complexity compared to 18-525.

Prerequisites: (18-213 and 18-220 and 18-240 and 18-290 and 18-422) OR (18-213 and 18-220 and 18-240 and 18-290 and 18-622) OR (18-213 and 18-220 and 18-240 and 18-290 and 18-623)

Last Modified: 2024-11-20 12:14PM

Semesters offered:

• Spring 2025
• Spring 2024
• Spring 2016
• Fall 2014
• Fall 2013
• Fall 2010
• Fall 2009
• Fall 2008
• Fall 2007
• Spring 2007
• Spring 2006
• Spring 2005
• Spring 2004
• Spring 2003
• Spring 2002
• Spring 2001
• Spring 2000
• Spring 1999
• Spring 1998
• Spring 1997