Carnegie Mellon University

Electrical and Computer Engineering

College of Engineering

Course Information

18-765: Digital Systems Testing and Testable Design




For this course, time- and topic-indexed videos of lecture, homework, projects, etc. will be available from the online learning portal/website. In addition to these resources, two 1-hour live sessions are scheduled per week for recitation. Each student is strongly urged to attend one of these two sessions each week, either remotely or in the classroom on the Carnegie-Mellon Pittsburgh campus. This course examines in depth the theory and practice of fault analysis, test generation, and design for testability for digital ICs and systems. The topics to be covered include circuit and system modeling; fault sources and types; the single stuck-line (SSL), delay, and functional fault models; fault simulation methods; automatic test pattern generation (ATPG) algorithms for combinational and sequential circuits, including the D-algorithm, PODEM, FAN, and the genetic algorithm; testability measures; design-for-testability; scan design; test compression methods; logic-level diagnosis; built-in self-testing (BIST); VLSI testing issues; and processor and memory testing. Advance research issues, including topics on MEMS and mixed-signal testing are also discussed. 4 hours of lecture per week.

Prerequisites: 18-240 and 15-210 and (18-340 or 18-341) Senior or graduate standing required.

Last Modified: 2018-11-09 4:27PM

Current session:

This course is currently being offered.

Semesters offered:

  • Fall 2018
  • Fall 2017
  • Spring 2016
  • Fall 2015
  • Spring 2015
  • Summer-1/All 2014
  • Spring 2014
  • Fall 2013
  • Fall 2012
  • Fall 2011
  • Fall 2010
  • Fall 2009
  • Fall 2008
  • Fall 2007
  • Fall 2006
  • Fall 2005
  • Fall 2004
  • Spring 2004
  • Spring 2003
  • Spring 2002
  • Fall 2001
  • Fall 2000
  • Fall 1999
  • Fall 1998
  • Fall 1997